Configuration Options for 18F1330

   Oscillator Selection:
     OSC = LP             LP Oscillator
     OSC = XT             XT Oscillator
     OSC = HS             HS Oscillator
     OSC = EC             External Clock on OSC1, OSC2 as Fosc/4
     OSC = ECIO           External Clock on OSC1, OSC2 as RA6
     OSC = HSPLL          HS + PLL
     OSC = RCIO           External RC on OSC1, OSC2 as RA6
     OSC = INTIO2         Internal RC, OSC1 as RA7, OSC2 as RA6
     OSC = INTIO1         Internal RC, OSC1 as RA7, OSC2 as Fosc/4
     OSC = RC             External RC on OSC1, OSC2 as Fosc/4

   Fail Safe Clock Monitor:
     FSCM = OFF           Fail Safe Clock Monitor disabled
     FSCM = ON            Fail Safe Clock Monitor enabled

   Internal External Switch Over mode:
     IESO = OFF           Internal External Switch Over mode disabled
     IESO = ON            Internal External Switch Over mode enabled

   Power-Up Timer:
     PWRT = ON            Enabled
     PWRT = OFF           Disabled

   Brown-Out Reset:
     BOR = OFF 		Brown-out Reset disabled in hardware and software
     BOR = SBORENCTRL 	Brown-out Reset enabled and controlled by software (SBOREN is enabled)
     BOR = BOACTIVE 	Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
     BOR = BOHW 	Brown-out Reset enabled in hardware only (SBOREN is disabled)

   Brown Out Voltage:
     BORV = 0 		Maximum setting
     BORV = 1 
     BORV = 2 
     BORV = 3 		Minimum setting

   Watchdog Timer:
     WDT = OFF            Disabled
     WDT = ON             Enabled

   Watchdog Postscaler:
     WDTPS = 1            1:1
     WDTPS = 2            1:2
     WDTPS = 4            1:4
     WDTPS = 8            1:8
     WDTPS = 16           1:16
     WDTPS = 32           1:32
     WDTPS = 64           1:64
     WDTPS = 128          1:128
     WDTPS = 256          1:256
     WDTPS = 512          1:512
     WDTPS = 1024         1:1024
     WDTPS = 2048         1:2048
     WDTPS = 4096         1:4096
     WDTPS = 8192         1:8192
     WDTPS = 16384        1:16384
     WDTPS = 32768        1:32768

High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit):
    HPOL = LOW 		PWM1, PWM3 and PWM5 are active-low
    HPOL = HIGH 	PWM1, PWM3 and PWM5 are active-high (default)

Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit):
    LPOL = LOW 		PWM0, PWM2 and PWM4 are active-low
    LPOL = HIGH 	PWM0, PWM2 and PWM4 are active-high (default)

PWM Output Pins Reset State Control bit:
   PWMPIN = ON 		PWM outputs drive active states upon Reset
   PWMPIN = OFF 	PWM outputs disabled upon Reset

FLTA MUX bit:
   FLTAMX = RA7 	FLTA input is muxed onto RA7
   FLTAMX = RA5 	FLTA input is muxed onto RA5

T1OSO/T1CKI MUX bit:
   T1OSCMX = LOW 	T1OSO/T1CKI pin resides on RB2
   T1OSCMX = HIGH 	T1OSO/T1CKI pin resides on RA6

Master Clear Enable bit:
   MCLRE = OFF 		RA5 input pin enabled, MCLR pin disabled
   MCLRE = ON 		MCLR pin enabled, RA5 input pin disabled

Stack Overflow/Underflow Reset Enable bit:
   STVREN = OFF 	Reset on stack overflow/underflow disabled
   STVREN = ON 		Reset on stack overflow/underflow enabled

Boot Block Size Select bits:
   BBSIZ = BB256 	256 Words (512 Bytes)
   BBSIZ = BB512 	512 Words (1024 Bytes)
   BBSIZ = BB1K 	1K Words (2048 Bytes)

Extended Instruction Set Enable bit:
   XINST = OFF 		Instruction set extension and Indexed Addressing mode disabled
   XINST = ON 		Instruction set extension and Indexed Addressing mode enabled

Background Debugger Enable bit:
   DEBUG = ON 		Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
   DEBUG = OFF 		Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

Code Protection bit Block 0 (00400-007FF):
   CP0 = ON 		Block 0 is code-protected
   CP0 = OFF 		Block 0 is not code-protected

Code Protection bit Block 1 (00800-00FFF):
   CP1 = ON 		Block 1 is code-protected
   CP1 = OFF 		Block 1 is not code-protected

Code Protection bit (Boot Block Memory Area):
   CPB = ON 		Boot Block is code-protected
   CPB = OFF 		Boot Block is not code-protected

Code Protection bit (Data EEPROM):
   CPD = ON 		Data EEPROM is code-protected
   CPD = OFF 		Data EEPROM is not code-protected

Write Protection bit Block 0 (00400-007FF):
   WRT0 = ON 		Block 0 is write-protected
   WRT0 = OFF 		Block 0 is not write-protected

Write Protection bit Block 1 (00800-00FFF):
   WRT1 = ON 		Block 1 is write-protected
   WRT1 = OFF 		Block 1 is not write-protected

Write Protection bit (Boot Block Memory Area):
   WRTB = ON 		Boot Block is write-protected
   WRTB = OFF 		Boot Block is not write-protected

Write Protection bit (Configuration Registers):
   WRTC = ON 		Configuration registers are write-protected
   WRTC = OFF 		Configuration registers are not write-protected

Write Protection bit (Data EEPROM):
   WRTD = ON 		Data EEPROM is write-protected
   WRTD = OFF 		Data EEPROM is not write-protected

Table Read Protection bit Block 0 (00400-007FF):
   EBTR0 = ON 		Block 0 is protected from table reads executed in other blocks
   EBTR0 = OFF 		Block 0 is not protected from table reads executed in other blocks

Table Read Protection bit Block 1 (00800-00FFF):
   EBTR1 = ON 		Block 1 is protected from table reads executed in other blocks
   EBTR1 = OFF 		Block 1 is not protected from table reads executed in other blocks

Table Read Protection bit (Boot Block Memory Area):
   EBTRB = ON 		Boot Block is protected from table reads executed in other blocks
   EBTRB = OFF 		Boot Block is not protected from table reads executed in other blocks